Functional Safety Manager (FSM) and Corporate Application Manager
Engineers often want to jump into quantitative analysis before doing the necessary upfront qualitative thought required to underpin a valid FMEDA. This session describes how chip and semiconductor IP FMEA should start from an overall architecture that is modular and hierarchal, which allows for “pin level” failure mode analysis at the module level which can then be integrated to describe top-level failure modes and coverage.
This session provides “lessons learned” regarding the ISO 26262 deliverables that Tier-1s and semiconductor vendors should expect from their suppliers. Practical advice is given regarding DIA and Safety Manual contents, as well as FMEDA expectations for configurable IP.